This invention relates to a transversal filter for use in a waveform equalization circuit in a digital communication system and, more particularly, to a transversal filter of a parallel processing type.
In general, the transversal filter is used in a waveform shaping filter such as the waveform equalization circuit in the digital communication system or an interference canceller. The transversal filter has been digitized and put to practical use due to miniaturization of the device, low power consumption, and adjustmentless. In addition, in order to be operable at a high speed, it has been made a proposal to make a plurality of transversal filters process in parallel to construct the transversal filter of the parallel processing type. Such a transversal filter of the parallel processing type has been disclosed, for example, in Japanese Unexamined Patent Prepublication No. 190033/90.
A conventional transversal filter is supplied with an input signal having an input data rate. The input signal may be a baseband digital signal which is obtained by demodulating and decision a digital modulated signal. The transversal filter filters the input signal into an output signal in response to first through J-th tap gains, where J represents a first positive integer which is not less than two. The output signal also has an output data rate equal to the input data rate. The transversal filter comprises a delay circuit which has first through J-th taps. The input signal is supplied to the delay circuit. The delay circuit comprises first through (J-1)-th delay units each of which is placed between two taps of the first through the J-th taps. Each of the first and the (J-1)-th delay units provides a unit delay which is substantially equal to a reciprocal of the input data rate. The first through the J-th taps of the delay circuit produce first through J-th tap signals, respectively.
The first through the J-th tap signals are supplied to first and second latch circuits. The first latch circuit latches the first through the J-th tap signals at each odd time slot of the input signal and holds these signals during a time duration corresponding to two time slots to produce first through J-th primary latched signals. Likewise, the second latch circuit latches the first through the J-th tap signals at each even time slot of the input signal and holds these signals during the time duration corresponding to the two time slots to produce first through J-th subsidiary latched signals.
The first through the J-th primary latched signals are supplied to a first calculation circuit. The first calculation circuit comprises first through J-th primary multiplying circuits and a first adding circuit. The first through the J-th primary multiplying circuits are supplied with the first through the J-th primary latched signals. The first through the J-th tap gains are supplied to the first through the J-th primary multiplying circuits, respectively. The first through the J-th primary multiplying circuits multiplies the first through the J-th primary latched signals by the first through the J-th tap gains to produce first through J-th primary product signals, respectively. The first through the J-th primary product signals are supplied to the first adding circuit. The first adding circuit adds up J terms of the first through the J-th primary product signals to produce a first addition result signal indicative of a first addition result of the J terms.
Likewise, the first through the J-th subsidiary latched signals are supplied to a second calculation circuit. The second calculation circuit comprises first through J-th subsidiary multiplying circuits and a second adding circuit. The first through the J-th subsidiary multiplying circuits are supplied with the first through the J-th subsidiary latched signals. The first through the J-th tap gains are supplied to the first through the J-th subsidiary multiplying circuits, respectively. The first through the J-th subsidiary multiplying circuits multiply the first through the J-th subsidiary latched signals by the first through the J-th tap gains to produce first through J-th subsidiary product signals, respectively. The first through the J-th subsidiary product signals are supplied to the second adding circuit. The second adding circuit adds up J terms of the first through the J-th subsidiary product signals to produce a second addition result signal indicative of a second addition result of the J terms.
The first and the second addition result signals are supplied to a parallel-serial converter. The parallel-serial converter carries out a parallel-serial conversion on or couples the first and the second addition result signals to produce a serial converted signal as the output signal.
As apparent from the above description, the transversal filter produces the output signal which is equalized thereby. In the conventional transversal filter, the first and the second latch circuits distribute input elements of the input signal into the first through the J-th primary latched signals and the first through the J-th subsidiary latched signals at alternative timings. In other words, each of the first and the second latch circuits serves as a serial-parallel converter for converting the input signal into J latched signals each of which has a data rate equal to a half times as large as the input data signal of the input signal. Accordingly, the first and the second calculation circuits carry out the parallel processing at a low operational speed which is equal to a half of the output data rate of the output signal. However, each of the first through the (J-1)-th delay units must carry out a delay operation at an operational speed equal to the input data rate of the input signal. As a result, the conventional transversal filter is defective in that the input data rate of the input signal and the operational speed of the transversal filter are restricted by the operational speed of the first through the (J-1)-th delay units.